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STLC60135
TOSCATM ADSL DMT TRANSCEIVER
DTM modem for ADSL, compatible with the following standards: - ANSI T1.413 Issue 2 - ITU-T G.992.1 (G.dmt) - ITU-T G.992.2 (G.lite) Same chip for both ATU-C and ATU-R Supports either ATM (Utopia level 1 & 2) or bitstream interface 16 bit multiplexed microprocessor interface (little and big endian compatibility) Analog Front End management Dual latency paths: fast and interleaved ATM's PHY layer: cell processing (cell delineation, cell insertion, HEC) ADSL's overhead management Reed Solomon encode/decode Trellis encode/decode (Viterbi) DMT mapping/ demapping over 256 carriers Fine (2ppm) timing recover using Rotor and Adaptative Frequency Domain Equalizing Time Domain Equalization Front end digital filters 0.35m HCMOS6 Technology 144 pin PQFP package Power Consumption 1 Watt at 3.3V Figure 1. Block Diagram
TEST SIGNALS
PQFP144 ORDERING NUMBER: STLC60135
Applications ATU-C: DSLAM, Routers at Central Office ATU-R: Routers at SOHO, stand-alone modems, PC mother boards General Description The STLC60135 is the DMT modem and ATM framer of the STMicroelectronics ToscaTM chipset. When coupled with STLC60134 analog front-end and an external controller running dedicated firmware, the product fulfils ANSI T1.413 "Issue 2" DMT ADSL specification. The STLC60135 may be used at both ends of ADSL loop: ATU-C and ATU-R. The chip supports UTOPIA level 1 and UTOPIA level 2 interface and a non ATM synchronous bit-stream interface.
CLOCK
TEST MODULE
DATA SYMBOL TIMING UNIT
VCXO
STM AFE INTERFACE DSP
FRONT-END
FFT/IFFT ROTOR
TRELLIS CODING MAPPER/ DEMAPPER
GENERIC TC REED/ SOLOMON
INTERFACE MODULE UTOPIA
AFE CONTROL
AFE
CONTROL INTERFACE
CONTROLLER INTERFACE
ATM SPECIFIC TC
CONTROLLER BUS
GENERAL PURPOSE I/Os
D98TL315
September 1999
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STLC60135
The STLC60135 can be splitted up into two different sections. The physical one performs the DMT modulation, demodulation, Reed-Solomon encoding, bit interleaving and 4D trellis coding. The ATM section embodies framing functions for the generic and ATM Transmission Convergence (TC) layers. The generic TC consists of data scrambling and Reed Solomon error corrections, with and without interleaving. The STLC60135 is controlled and programmed by an external controller (ADSL Transceiver Controller, ATC) that sets the programmable coefficients. The firmware controls the initialization phase and carries out the consequent adaptationoperations. ABSOLUTE MAXIMUM RATINGS
Symbol VDD Ptot Tamb Parameter Supply Voltage Total Power Dissipation Ambient Temperature 1m/s airflow Min 3.0 -40 Typ 3.3 900 Max 3.6 1400 85 Unit V mW C
Transient Energy Capabilities ESD ESD (Electronic Discharged) tests have been performed for the Human Body Model (HBM) and for the Charged Device Model (CDM). The pins of the device are to be able to withstand minimum 1500V for the HBM and minimum 250V for CDM. Latch-up The maximum sink or source current from any pin is limited to 100mA to prevent latch-up.
Figure 2. Pin Connection
VDD AFTXD_3 AFTXD_2 VSS AFTXD_1 AFTXD_0 IDDq VDD AFTXED_3 AFTXED_2 VSS AFTXED_1 AFTXED_0 VDD CTRLDATA MCLK CLWD VSS AFRXD_3 AFRXD_2 AFRXD_1 AFRXD_0 VDD PDOWN GP_OUT TESTSE TRSTB VSS TCK VDD TMS TDO TDI SLT_FRAME_S SLT_REQ_S VSS
144143142141140139138137136135134133132131130129128127126125124123122121120119118117116115114113112111110109 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
VSS AD_0 AD_1 AD_2 VDD AD_3 AD_4 VSS AD_5 AD_6 VDD AD_7 AD_8 AD_9 VSS AD_10 AD_11 VDD AD_12 VSS PCLK VDD AD_13 AD_14 AD_15 VSS BE1 ALE VDD CSB WR_RDB RDYB OBC_TYPE INTB RESETB VSS
VDD SLT_REQ_F SLT_DAT_S0 SLT_DAT_S1 SLT_DAT_F0 SLT_DAT_F1 VSS SLT_FRAME_F SLAP_CLOCK SLR_VAL_F SLR_DAT_F0 SLR_DAT_F1 SLR_VAL_S VDD SLR_DAT_S0 SLR_DAT_S1 SLR_FRAME_S VSS SLR_FRAME_F U_TX_ADDR_0 U_TX_ADDR_1 U_TX_ADDR_2 VDD U_TX_ADDR_3 U_TX_ADDR_4 U_TX_DATA_0 U_TX_DATA_1 VDD U_TX_DATA_2 U_TX_DATA_3 U_TX_DATA_4 U_TX_DATA_5 VDD U_TX_DATA_6 U_TX_DATA_7 VSS
VDD U_RXDATA_0 U_RXDATA_1 VSS U_RXDATA_2 U_RXDATA_3 VDD U_RXDATA_4 U_RXDATA_5 VSS U_RXDATA_6 U_RXDATA_7 VDD U_RX_ADDR_0 U_RX_ADDR_1 U_RX_ADDR_2 U_RX_ADDR_3 VSS U_RX_ADDR_4 GP_IN0 VDD GP_IN1 VSS U_RX_REFB U_TX_REFB VDD U_RXCLK U_RXSOC U_RXCLAV U_RXENBB VSS U_TXCLK U_TXSOC U_TX_CLAV U_TXENBB VDD
D98TL367B
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STLC60135
PIN FUNCTIONS
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 Name VSS AD_0 AD_1 AD_2 VDD AD_3 AD_4 VSS AD_5 AD_6 VDD AD_7 AD_8 AD_9 VSS AD_10 AD_11 VDD AD_12 VSS PCLK VDD AD_13 AD_14 AD_15 VSS BE1 ALE VDD CSB WR_RDB RDYB OBC_TYPE INTB RESETB VSS VDD U_RxData_0 U_RxData_1 VSS U_RxData_2 U_RxData_3 VDD OZ OZ VDD VDD BD8SRC BD8SRC B B OZ OZ VDD VDD BD8SRC BD8SRC B B I I OZ I-PD O I VDD VDD VDD VDD VDD VDD IBUF IBUF BT4CR IBUF IBUF IBUF I I O I O I I I VDD VDD IBUF IBUF I C B B B VDD VDD VDD BD8SCR BD8SCR BD8SCR B B B I VDD IBUF I B VDD BD8SCR B B B VDD VDD BD8SCR BD8SCR B B B B B VDD VDD VDD BD8SCR BD8SCR BD8SCR B B B B B VDD VDD BD8SCR BD8SCR B B B B VDD VDD BD8SCR BD8SCR B B B B B VDD VDD VDD BD8SCR BD8SCR BD8SCR B B B Type Supply Driver BS 0V Ground Data 0 Data 1 Address / Data 2 (VSS + 3.3V) Power Supply Address / Data 3 Address / Data 4 0V Ground Address / Data 5 Address / Data 6 (VSS + 3.3V) Power Supply Address / Data 7 Address / Data 8 Address / Data 9 0V Ground Address / Data 10 Address / Data 11 (VSS + 3.3V) Power Supply Address / Data 12 0V Ground Processor clock (VSS + 3.3V) Power Supply Address / Data 13 Address / Data 14 Address / Data 15 0V Ground Address 1 Address Latch (VSS + 3.3V) Power Supply Chip Select Specifies the direction of the access cycle Controls the ATC bus cycle termination ATC Mode Selection (0 = i960; 1 = generic) Requests ATC interrupt service Hard reset 0V Ground (VSS + 3.3V) Power Supply Utopia RX Data 0 Utopia RX Data 1 0V Ground Utopia RX Data 2 Utopia RX Data 3 (VSS + 3.3V) Power Supply Function
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STLC60135
PIN FUNCTIONS (continued)
Pin 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 Name Type Supply U_RxData_4 OZ VDD U_RxData_5 OZ VDD VSS U_RxData_6 OZ VDD U_RxData_7 OZ VDD VDD U_RxADDR_0 I VDD U_RxADDR_1 I VDD U_RxADDR_2 I VDD U_RxADDR_3 I VDD VSS U_RxADDR_4 I VDD GP_IN_0 I-PD VDD VDD GP_IN_1 I-PD VDD VSS U_RxRefB O VDD U_TxRefB I VDD VDD U_Rx_CLK I VDD U_Rx_SOC OZ VDD U_RxCLAV OZ VDD U_RxENBB I VDD VSS U_Tx_CLK I VDD U_Tx_SOC I VDD U_TxCLAV OZ VDD U_TxENBB I VDD VDD VSS U_TxData_7 I VDD U_TxData_6 I VDD VDD U_TxData_5 I VDD U_TxData_4 I VDD U_TxData_3 I VDD U_TxData_2 I VDD VDD U_TxData_1 I VDD U_TxData_0 I VDD U_TxADDR_4 I VDD U_TxADDR_3 I VDD VDD U_TxADDR_2 I VDD U_TxADDR_1 I VDD U_TxADDR_0 I VDD SLR_ FRAME_F O VDD VSS Driver BD8SRC BD8SRC BD8SRC BD8SRC IBUF IBUF IBUF IBUF IBUF IBUFDQ IBUFDQ IBUF BT4CR IBUF BD8SCR BD8SCR IBUF IBUF IBUF BD8SCR IBUF BS B B B B I I I I I I I O I Function Utopia RX Data 4 Utopia RX Data 5 0V Ground Utopia RX Data 6 Utopia RX Data 7 (VSS + 3.3V) Power Supply Utopia RX Address 0 Utopia RX Address 1 Utopia RX Address 2 Utopia RX Address 3 0V Ground Utopia RX Address 4 General purpose input 0 (VSS + 3.3V) Power Supply General purpose input 1 0V Ground 8kHz clock to ATM device 8kHz clock from ATM device (VSS + 3.3V) Power Supply Utopia RX Clock Utopia RX Start of Cell Utopia RX Cell Available Utopia RX Enable 0V Ground Utopia TX Clock Utopia TX Start of Cell Utopia TX Cell Available Utopia TX Enable (VSS + 3.3V) Power Supply 0V Ground Utopia TX Data 7 Utopia TX Data 6 (VSS + 3.3V) Power Supply Utopia TX Data 5 Utopia TX Data 4 Utopia TX Data 3 Utopia TX Data 2 (VSS + 3.3V) Power Supply Utopia TX Data 1 Utopia TX Data 0 Utopia TX Address 4 Utopia TX Address 3 (VSS + 3.3V) Power Supply Utopia TX Address 2 Utopia TX Address 1 Utopia TX Address 0 Frame Identifier Fast 0V Ground
IBUF IBUF IBUF IBUF IBUF IBUF IBUF IBUF IBUF IBUF IBUF IBUF IBUF BT4CR
I I I I I I I I I I I I I
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STLC60135
PIN FUNCTIONS (continued)
Pin 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 Name SLR_FRAME_S SLR_DATA_S_1 SLR_DATA_S_0 VDD SLR_VAL_S SLR_DATA_F_1 SLR_DATA_F_0 SLR_VAL_F SLAP_CLOCK SLT_FRAME_F VSS SLT_DATA_F_1 SLT_DATA_F_0 SLT_DATA_S_1 SLT_DATA_S_0 SLT_REQ_F VDD VSS SLT_REQ_S STL_FRAME_S TDI TDO TMS VDD TCK VSS TRSTB TESTSE GP_OUT PDOWN VDD AFRXD_0 AFRXD_1 AFRXD_2 AFRXD_3 VSS CLWD MCLK CTRLDATA VDD AFTXED_0 AFTXED_1 VSS AFTXED_2 AFTXED_3 VDD IDDq Type Supply O VDD O VDD O VDD O O O O O O I I I I O VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD Driver BT4CR BT4CR BT4CR BT4CR BT4CR BT4CR BT4CR BT4CR BT4CR IBUFDQ IBUFDQ IBUFDQ IBUFDQ BT4CR BS Function Receive Frame Identifier Interleaved Receive Data Interleave 1 Receive Data Interleave 0 (VSS + 3.3V) Power Supply Receive Data Valid Indicator Interleaved Receive Data Fast 1 Receive Data Fast 0 Receive Data Valid Indicator Fast Clock for SLAP I/F Transmit Start of frame Indicator Fast 0V Ground Transmit Data Fast 1 Transmit Data Fast 0 Transmit Data Interleave 1 Transmit Data Interleave 0 Transmit Byte Request Fast (VSS + 3.3V) Power Supply 0V Ground Transmit Byte Request Interleaved Transmit Start of frame Indication Interleaved JTAG I/P JTAG O/P JTAG Made Select (VSS + 3.3V) Power Supply JTAG Clock 0V Ground JTAG Reset Enables scan test mode General purpose output Power down analog front end (Reset) (VSS + 3.3V) Power Supply Receive data nibble Receive data nibble Receive data nibble Receive data nibble 0V Ground Start of word indication Master clock Serial data Transmit channel (VSS + 3.3V) Power Supply Transmit echo nibble Transmit echo nibble 0V Ground Transmit echo nibble Transmit echo nibble (VSS + 3.3V) Power Supply Test pin, active high
O O I-PU OZ I-PU I-PD I-PD I O O I I I I I I O O O O O I
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
BT4CR BT4CR IBUFUQ BT4CR IBUFUQ IBUFDQ IBUFDQ IBUF BD8SCR BT4CR IBUF IBUF IBUF IBUF IBUF IBUF BT4CR BT4CR BT4CR BT4CR BT4CR IBUF
none O O I I I I I C O O O O O none
5/25
STLC60135
PIN FUNCTIONS (continued)
Pin 139 140 141 142 143 144 Name AFTXD_0 AFTXD_1 VSS AFTXD_2 AFTXD_3 VDD Type Supply O VDD O VDD O O VDD VDD Driver BT4CR BT4CR BT4CR BT4CR BS O O O O Function Transmit data nibble Transmit data nibble 0V Ground Transmit data nibble Transmit data nibble (VSS + 3.3V) Power Supply
I/O DRIVER FUNCTION
Driver BD4CR BD8SCR IBUF IBUFDQ IBUFUQ Function CMOS bidirectional, 4mA, slew rate control CMOS bidirectional, 8mA, slew rate control, Schmitt trigger CMOS input CMOS input, pull down, IDDq control CMOS input, pull up, IDDq control
PIN SUMMARY
Mnemonic Type BS Type Signals (VSS + 3.3V) Power Supply 0V Ground I I I I I OZ O IO I-PD I-PU OZ I-PD I-PU I-PD C I I I I O O B I 1 1 1 1 1 1 1 16 1 1 1 1 1 1 Used to latch the address of the internal register to be accessed Processor clock Chip selected to respond to bus cycle Address 1 (not multiplexed) Specifies the direction of the access cycle Controls the ATC bus cycle termination Requests ATC interrupt service Multiplexed Address/Data bus Select between i960 (0) or generic (1) controller interface refer to section Function
Power Supply
VDD VSS
ATC Interface
ALE PCLK CSB BE1 WR_RDB RDYB INTB AD OBC_TYPE TDI TDO TCK TMS TRSTB
Test Access Part Interface
Analog Front End Interface
AFRXD AFTXD AFTXED CLWD PDOWN CTRLDATA MCLK I O O I O O I I O O I O O C 4 4 4 1 1 1 1 Receive data nibble Transmit data nibble Transmit echo nibble Start of word indication Power down analog front end Serial data transmit channel Master clock
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STLC60135
PIN SUMMARY (continued)
Mnemonic U_RxData U_TxData U_RxADDR U_TxADDR U_RxCLAV U_TxCLAV U_RxENBB U_TxENBB U_RxSOC U_TxSOC U_RxCLK U_TxCLK U_RxRefB U_TxRefB Type OZ I I I OZ OZ I-TTL I-TTL OZ I-TTL I-TTL I-TTL O I-TTL BS Type B I I I O O I I O I C C O I Signals 8 8 5 5 1 1 1 1 1 1 1 1 1 1 Function Receive interface Data Transmit interface Data Receive interface Address Transmit interface Address Receive interface Cell Available Transmit interface Cell Available Receive interface Enable Transmit interface Enable Receive interface Start of Cell Transmit interface Start of Cell Receive interface Utopia Clock Transmit interface Utopia Clock 8kHz reference clock to ATM device 8kHz reference clock from ATM device
ATM UTOPIA Interface
ATM SLAP Interface
SLR_VAL_S SLR_VAL_F SLR_DATA_S SLR_DATA_F SLT_REQ_S SLT_REQ_F SLT_DATA_S SLT_DATA_F SLAP_CLOCK SLR_FRAME_I SLT_FRAME_I SLR_FRAME_F SLT_FRAME_F O O O O O O I I O O O O O 1 1 2 2 1 1 2 2 1 1 1 1 1
Miscellaneous
GP_IN GP_OUT RESETB TESTSE IDDq I I-PU I-PD I-TTL O OZ IO BS cell I O B C = = = = = = = = = = = = I-PD O I I I I O I none none 2 1 I none none General purpose input General purpose output Hard reset Enable scan test mode Test pin, active high
Input, CMOS levels Input with pull-up resistance, CMOS levels Input with pull-down resistance, CMOS levels Input TTL levels Push-pull output Push-pull output with high-impedance state Input / Tristate Push-pull output Boundary-Scan cell Input cell Output cell Bidirectional cell Clock 7/25
STLC60135
Main Block Description The following drawings describe the sequence of functions performed by the chip. DSP Front-End The DSP Front-End contains 4 parts in the receive direction: the Input Selector, the Analog Front-End Interface, the Decimator and the Time Equalizer. The input selector is used internally to enable test loopbacks inside the chip. The Analog Front-End lnterface transfers 16-bit words, multiplexed on 4 input/output signals. Word transfer is carried out in 4 clock cycles. The Decimator receive 16-bits samples at 8.8 MHz (as sent by the Analog Front-End chip: STLC60134) and reduces this rate to 2.2 MHz. The Time Equalizer (TEQ) module is a FIR filter with programmable coefficients. Its main purpose is to reduce the effect of Inter-Symbol Interferences (ISI) by shortening the channel impulse response. Both the Decimator and TEQ can be bypassed. In the transmit direction, the DSP Front-End includes: sidelobe filtering, clipping, delay equalization and interpolation. The sidelobe filtering and Figure 3. DSP Front-End Receive delay equalization are implemented by IIR Filters, reducing the effect of echo in FDM systems. Clipping is a statistical process limiting the amplitude of the output signal, optimizing the dynamic range of the AFE. The interpolator receives data at 2.2 MHz and generates samples at a rate of 8.8 MHz. DMT Modem This module is a programmable DSP unit. Its instruction set enables the basic functions of the DMT algorithm like FFT, IFFT, Scaling, Rotor and Frequency Equalization (FEQ) in compliance with ANSI T1.413 specifications. In the RX path, the 512-point FFT transforms the time-domain DMT symbol into a frequency domain representation which can be further decoded by the subsequent demapping stages. In other words, the Fast Fourier Transform process is used to transform from time domain to frequency domain (receive path). On ATU-C side, 128 time samples are processed. On ATU-R side, 1024 time samples are processed. After the first stage time domain equalization and FFT block an ICI (InterCarrier Interference) free information stream turns out. Figure 4. DSP Front-End Transmit
BYPASS
FROM ANALOG FRONT-END
IN SELECT
AFE I/F
DEC
TEQ
TO DMT MODEM
FROM DMT MODEM
Filtering Clipping Delay Equalizer
Interpolator
AFE I/F
OUT SELECT
TO ANALOG FRONT END
D98TL382
D98TL372A
Figure 5. DMT Modem (Rx & Tx)
TRELLIS CODING DECODING
TO/FROM DSP FE
FFT IFFT
FEQ FTG
ROTOR
MAPPER DEMAPPER
TO/FROM TC
FEQ COEFFICIENTS
MONITOR
FEQ UPDATE
MONITOR INDICATIONS
D98TL316A
8/25
STLC60135
This stream is still affected by carrier specific channel distortion resulting in an attenuation of the signal amplitude and a rotation of the signal phase. To compensate, a Frequency domain equalizer (FEQ) and a Rotor (phase shifter) are implemented. The frequency domain equalisation performs an operation on the received vector in order to match it with the associated point in the constellation. The coefficient used to perform the equalisation are floating point, and may be updated by hardware or software, using a mechanism of active and inactive table to avoid DMT synchro problems. In the transmit path, the IFFT reverses the DMT symbol from frequency domain to time domain. The IFFT block is preceded by Fine Tune Gain (FTG) and Rotor stages, allowing for a compensation of the possible frequency mismatch between the master clock frequency and the transmitter clock frequency (which may be locked to another reference). The Inverse Fast Fourier Transform process is used to transform from frequency domain to time domain ( transmit path). On ATU-C side, 512 frequencies are processed, giving 1024 samples in the time domain. On ATU-R side, 256 positive frequencies are processed, giving 512 samples in the time domain. The FFT module is a slave DSP engine controlled by the firmware running on an external controller. It works off line and communicates with other blocks through buffers controlled by the "Data Symbol Timing Unit". The DSP executes a program stored in a RAM area, which constitutes a flexible element that allows for future system enhancements. DPLL The Digital PLL module receives a metric for the phase error of the pilot tone. In general, the clock frequencies at the ends (transmitter and receiver) do not match exactly. The phase error is filtered and integrated by a low pass filter, yielding an estimation of the frequency offset. Various processes can use this estimate to deal with the frequency mismatch. Figure 6. Generic TC Layer Functions
INDICATION BITS AOC EOC
In particular, small accumulated phase error can be compensated in the frequency domain by a rotation of the received code constellation (Rotor). Larger errors are compensated in the time domain by inserting or deleting clock cycles in the sample input sequence. Eventually that leads to achieve less than 2ppm between the two ends. Mapper/Demapper, Monitor, Trellis Coding, FEQ Update The Demapper converts the constellation points computed by the FFT to a block of bits. This means to identify a point in a 2D QAM constellation plane. The Demapper supports Trellis coded demodulation and provides a Viterbi maximum likelihood estimator. When the Trellis is active, the Demapper receives an indication for the most likely constellation subset to be used. In the transmit direction, the mapper receives a bit stream from the Trellis encoder and modulates the bit stream on a set of carriers (up to 256). It generate coordinates for 2n QAM constellation, where n < 15 for all carriers. The Mapper performs the inverse operation, mapping a block of bits into one constellation point (in a complex x+jy representation) which is passed to the IFFT block. The Trellis Encoder generates redundant bits to improve the robustness of the transmission, using a 4-Dimensional Trellis Coded Modulation scheme. This feature can be disabled. The Monitor computes error parameters for carriers specified in the Demapper process. Those parameters can be used for updates of adaptive filters coefficients, clock phase adjustments, error detection,etc. A series of values is constantly monitored, such as signal power, pilot phase deviations, symbol erasures generation, loss of frame,etc. Generic TC Layer Functions These functions relate to byte oriented data streams. They are completely described in ANSI T 1.4 13. Additions described in the Issue 2 of
TO/FROM DEMAPPER
DATA PATX MERGER
FAST
F RS CODING DECODING I
PMD SCRAMBLER DESCRAMBLER
F FRAMER DEFRAMER I
TO ATM TC
INTERLEAVER DE-INTERLEAVER
PMD SCRAMBLER DESCRAMBLER
D98TL317A
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STLC60135
this specification are also supported. The data received from the demapper may be split into two paths, one dedicated to an interleaved data flow the other one for a fast data flow. No external RAM is needed for the interleaved path. The interleaving/deinterleaving is used to increase the error correcting capability of block codes for error bursts. After deinterleaving (if applicable), the data flow enters a Reed-Solomon error correcting code decoder, able to correct a number of bytes containing bit errors. The decoder also uses the information of previous receiving stages that may have detected the errored bytes and have labelled them with an "erasure" indication". Each time the RS decoder detects and corrects errors in a RS codeword, an RS correction event is generated. The occurrence of such events can be signalled to the management layer. After the RS decoder, the corrected byte stream is descrambled in the PMD (Physical Medium Dependent) descramblers. Two descramblers are used, for interleaved and non-interleaved data flows. These are defined in ANSI T1.413. After descrambling, the data flows enter the Deframer that extracts and processes bytes to support Physical layer related functions according to ANSI T1.413. The ADSL frames indeed contain physical layer-related information in addition to the data passed to the higher layers. In particular, the deframer extracts the EOC (Embedded Operations Channel), the AOC (ADSL Overhead Control) and the indicators bits and passes them to the appropriate processing unit (e.g. the transceiver controller). The deframer also performs a CRC check (Cyclic Redundancy Check ) on the received frame and generates events in case of error detection. Event counters can be read by management processes. The outputs of the deframer are an interleaved and a fast data streams. These data streams can either carry ATM cells or another type of traffic. In the latter case, the ATM specific TC layer functional block, described hereafter, is bypassed and the data stream is directly presented at the input of the interface module. ATM Specific TC Layer Functions The 2 bytes streams (fast and slow) are received from the byte-based processing unit. When ATM cells are transported, this block provides basic cell functions such as cell synchronization, cell payload descrambling, idle/unassigned cell filter, cell Header Error Correction (HEC) and detection. The cell processing happens according to ITU-T I.163 standard. Provision is also made for BER measurements at this ATM cell level. When non cell oriented byte streams are transported, the cell processing unit is not active. The interface
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Figure 7. ATM Specific TC Layer Functions
BER
FAST FROM GENERIC TC
CELL SCRAMBLER DESCRAMBLER SYNCHRONIZER CELL SCRAMBLER DESCRAMBLER SYNCHRONIZER
HEC
CELL INSERTION/ FILTER
TO INTERFACE MODULE
SLOW
HEC
CELL INSERTION/ FILTER
BER
D98TL318A
Figure 8. Interface Module
FAST BYTE STREAM
SLAP
UTOPIA FAST ATM
LEVEL 1
UTOPIA LEVEL 2 FROM ATM TC UTOPIA SLOW ATM LEVEL 2 LEVEL 1
UTOPIA
SLOW BYTE STREAM
SLAP
D98TL319A
module collects cells (from the cell-based function module) or a Byte stream (from the deframer). Cells are stored in FIFO's (424 bytes or 8 cell wide, transmit buffers have the same size), from which they are extracted by 2 interface submodules, one providing a Utopia level 1 interface and the other a Utopia level 2 interface. Byte stream are dumped on the SLAP (Synchronous Link Access Protocol) interface. Only one type of interface can be enabled in a specific configuration. DMT Symbol Timing Unit (DSTU) The DSTU interfaces with various modules, like DSP FrontEnd, FFT/IFFT, Mapper/Demapper, RS , Monitor and Transceiver Controller. It consists of a real time and a scheduler modules. The real time unit generate a timebase for the DMT symbols (sample counter), superframes (symbol counter) and hyper-frames (sync counter). The timebases can be modified by various control features. They are continuously fine-tuned by the DPLL module.
STLC60135
The DSTU schedulers execute a program, controlled by program opcodes and a set of variables, the most important of which are real time counters. The transmit and receive sequencers are completely independent and run different programs. An independent set of variables is assigned to each of them. The sequencer programs can be updated in real time. STLC60135 interfaces Overview Figure 9. STLC60135 interfaces
AFE INTERFACE TO ADSL LINE (STLC60134)
Processor Interface (ATC) The STLC60135 is controlled and configured by an external processor across the processor interface. All programmable coefficients and parameters are loaded through this path. The ADSL initialization is also controlled by this interface Two interface types are supported; A generic asynchronous interface (i.e. PowerPC or any microprocessor interface) and a specific i960 interface. The choice is made by the OBC_TYPE pin. (0 selects i960 type interface, 1 selects generic access). Data and addresses are multiplexed. STLC60135 works in 16 bits data access, so address bit 0 is not used. Address bit 1 is not multiplexed with data. It has its own pin : BE1 Byte acces are not supported. Access cycle read or write are always in 16 bits data wide, ie bit address A0 is always zero value. The interrupt request pin to the processor is INTB, and is an Open Drain output. Tle STLC60135 supports both little and big endian. The default feature is big endian.
RESET PROCESSOR INTERFACE (ATC)
JTAG
STLC60135
CLOCK
D98TL368A DIGITAL INTERFACE UTOPIA/BITSTREAM INTERFACE
Figure 10. Processor Interface Read cycle i960 mode
Ta Tw Tw Tw Tw Td Tr Ta
PCLK
ALE
CSB
Wait
RDYB
ADDR DATAin
AD
ATC samples data
BE1 WR_RDB
ADD(1)
D98TL324A
(1): The RDYB output is continuously in tri-state, except for 2 cycles
Figure 11. Processor Interface Write Cycle i960 mode
Ta Tw Tw Tw Tw Td Tr Ta
PCLK
ALE
CSB
Wait
RDYB
ADDR DATA out
AD
STLC60135 samples data
BE1 WR_RDB
ADD(1)
D98TL325A
(1): The RDYB output is continuously in tri-state, except for 2 cycles
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STLC60135
The processor interface in i960 mode The i960 mode supports a synchronous bus interface protocol. Address and data are multiplexed. The processor is bus master and the STLC60135 is bus slave. Synchronous means that all signals are synchronous with the input clock PCLK pin. The bus cycles are directly started and driven by the processor. Addresses (BE1, AD[2..15]) have to be present before ATC asserts the ALE signal. STLC60135 latches the address on the falling edge of ALE signal. The RDYB output is synchronous to PCLK. A bus cycle consists of an Access cycle (Ta), Wait cycles (Tw), Data cycle (Td) and Recovery cycle (Tr). Processor Interface Pins and Functional Description i960 mode
Name Type AD[0...15] I/O BE1 I ALE I WR_RDB I PCLK I CSB I RDYB OZ INTB O Function Multiplexed Address/Data bus Address bit 1 Address Latch Enable Access direction: Write (1), Read (0) Processor Clock Chip Select Bus cycle ready indication Interrupt
Generic Interface This interface is suitable for a number of processors using a multiplexed Address/data bus. In this case, synchronisation of the input signals with PCLK pin is not necessary.
Figure 12. Generic Processor Interface Write Timing Cycle
Talew
ALE
Twr2cs
CSB
Tavs Tavh
AD(15-0)
Tale2cs Twr2d Twdvd Tdvh
WRB
Tcs2rdy Tcs2wr Twrw Tmclk
READY
Tcsre Trdy2wr
RDB
D98TL327
Figure 13. Generic Processor Interface Read Timing Cycle
Talew Tale2Z
ALE
Trd2cs
CSB
Tavs Tavh
AD(15-0)
Tale2cs Twr2d Twdvd Tdvh
RDB
Tcsrd Twrw
Tmclk
READY
Tcsrs Tcsre Trdy2dr
WRB
D98TL328
12/25
STLC60135
Generic processor interface Cycle Timing All AC characteristics are indicated for a 100pF capacitive load.
Symbol tr & tf Talew Tavs Tavh Tale2cs Tale2Z Tcs2rdy Tcsre Tcs2wr Twr2d Trdy2wr Tdvs Tdvh Twr2cs Tcs2rd Trdy2rd Trd2cs Tmclk Parameters Rise & Fall time (10% to 90%) ALE pulse width Address Valid setup time Address Valid Hold time ALE to CSB ALE to high Z state of address bus CSB to RDYB asserted Access Time CSB to WRB WRB to data RDYB to WRB data setup time data hold time WRB to CSB CSB to RDB RDY to RDB RDB to CSB Master clock Timing Min 12 10 10 0 50 60 900 0 15 0 10 1/2Tmclk -10 0 0 -10 Typ Max 3 Unit ns ns ns ns ns ns ns s ns ns ns ns ns ns ns ns ns
Tmclk
Figure 14. Waveforms
T alew
ALE
Tavs Tavh
AD(15:0)
D98TL326
Generic Processor Interface Pins and Functional Description
Name Type Function AD[0..15] I/O Multiplexed address / data bus ALE I Address Latch Enable RDB I Read cycle indication WRB I Write cycle indication CSB I Chip Select RDYB OZ Bus cycle ready indication INTB O Interrupt
Cells are stored in a fifo, 2 interfaces submodules can extract data from the fifo. Byte streams are dumped on the bitstream interface (with no fifo). 3 kinds of interface are allowed Utopia Level 1 Utopia Level 2 Bitstream based on a proprietary exchange The interface selection is programmed by writing the Utopia PHY address register. Only one interface can be enabled in a ST60135 configuration. Utopia Level 1 supports only one PHY device. Utopia Level 2 supports multi-PHY devices (See Utopia Level 2 specifications). Each buffer provides storage for 8 ATM cells (both directions for Fast and Interleaved channel).
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Digital interface ATM or serial Digital Interface for data to the loop before modulation and from the loop after demodulation. This interface collects cells (from the cell based function module) or a byte stream (from the deframer).
STLC60135
The Utopia Level 2 supports point to multipoint configurations by introducing an addressing capability and by making distinction between polling and selecting a device. Figure 15. ReceiveInterface
PHY ATM
RxREF* RxCLAV RxENB*
PHY RECEIVE
RxCLK RxDATA 8 RxSOC
CELL RECEIVE
Utopia Level 1 Interface The ATM forum takes the ATM layer chip as a reference. It defines the direction from ATM to physical layer as the Transmit direction. The direction from physical layer to ATM is the Receive direction. Figures 15 & 16 show the interconnection between ATM and PHY layer devices, the optional signals are not supported and not shown. The Utopia interface transfers one byte in a single clock cycle, as a result cells are transformed in 53 clock cycles. Both transmit and receive are synchronized on clocks generated by the ATM layer chip, and no specific relationship between receive and transmit clocks is required. In this mode, the STLC60135 can only support one data flow : either interleaved or fast . Figure 17. Timing (Utopia 1 Receive Interface)
D98TL330
Figure 16. Transmit Interface
PHY ATM LAYER
RxCLK
TxREF*
RxSOC
TxCLAV TxENB*
RxENB
PHY TRANSMIT
TxCLK TxDATA TxSOC
8
CELL TRANSMIT
RxDATA
X
H1
H2
P44
P45
P46
P47
P48
X
RxCLAV
D98TL369
D98TL370
Pin Description
Name RxClav Type Meaning O Receive Cell available Usage Signals to the ATM chip that the STLC60135 has a cell ready for transfer Signals to the STLC60135 that the ATM chip will sample and accept data during next clock cycle Gives the timing signal for the transfer, generated by ATM layer chip. ATM cell data, from STLC60135 chip to ATM chip, byte wide. Rx Data [7] is the MSB. Identifies the cell boundary on RxData 8 kHz clock transported over the network Remark Remains active for the entire cell transfer RxData and RxSOC could be tristate when RxEnb* is inactive (high). Active low signal
RxEnb*
I
Receive Enable
RxClk
I
Receive Byte Clock
RxData
O
Receive Data (8bits)
RxSOC
O
Receive Start Cell
RxRef *
O
Reference Clock
Indicate to the ATM layer chip that RxData contains the first valid byte of a cell. Active low signal
*Active low signal
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STLC60135
When RxEnb is asserted, the STLC60135 reads data from its internal fifo and presents it on RxData and RxSOC on each low-to-high transiPin Description
Name TxClav Type Meaning Usage O Transmit Cell available Signals to the ATM chip that the physical layer chip is ready to accept a complete cell I Transmit Enable Signals to the STLC60135 that TxData and TxSOC are valid I Transmit Byte Clock Gives the timing signal for the transfer, generated by ATM layer chip. I Transmit Data (8bits) ATM cell data, from ATM layer chip to STLC60135, byte wide. TxData [7] is the MSB. I Transmit Start of Cell Identifies the cell boundary on TxData I Reference Clock 8kHz clock from the ATM layer chip Remark Remains active for the entire cell transfer
tion of RxClk, ie the ATM layer chip samples all RxData and RxSOC on the rising edge of RxSOC on the rising edge of RxClk.
TxEnb* TxClk
TxData
TxSOC TxRef *
TxData contains the first valid byte of the cell.
*Active low signal
The STLC60135 samples TxData and TxSOC signals on the rising edge of TxClk, if TxEnb is asserted. TxClk, RxClk, AC electrical characteristics
Symbol F Tc Tj Trf L Parameters Clock frequency Clock duty cycle Clock peak to peak jitter Clock rise fall time Load Min 1.5 40 Max 25 60 5 4 100 Unit MHz % % ns pF
RxData, RxSOC, RxClav AC electrical characteristics
Symbol T7 T8 T9 T10 T11 Parameters Input set-up time to TxClk Hold time to Tx Clk Signal going low impedance to RxClk Signal going High impedance to RxClk Signal going low impedance to RxClk Signal going High impedance to RxClk Load Min 10 1 10 0 1 1 100 Max Unit ns ns ns ns ns ns pF
TxData, TxSOC, AC electrical characteristics
Symbol T5 T6 L Parameters Min Input set-up time to TxClk 10 Hold time to TxClk 1 Load Max Unit ns ns pF T12 L
100
Figure 18. Timing (Utopia 1 Transmit Interface)
TxCLK
TxSOC
TxENB
TxDATA
X
H1
H2
P44
P45
P46
P47
P48
X
TxCLAV
D98TL371
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STLC60135
Figure 19. Timing Specification (Utopia 1)
CLOCK
T5,T7 T6,T8
SIGNAL (at input) SIGNAL (highz)
T11 T9 T12 T10
D98TL331
DIGITAL INTERFACE Utopia Level 2 Interface The ATM forum takes the ATM layer chip as a reference. It defines the direction from ATM to physical layer as the Transmit direction. The direction from physical layer to ATM is the Receive direction. Figure 20 shows the interconnection between ATM and PHY layer devices, the optional signals are not supported and not shown. The UTOPIA interface transfers one byte in a single clock cycle, as a result cells are transferred in 53 clock cycles. Both transmit and receive interfaces are synchronized on clocks generated by the ATM layer chip, and no specific relationship between Receive and Transmit clock is assumed, they must be regarded as mutually asynchronous clocks. Flow Figure 20. Signal at Utopia Level 2 Interface
PHY
control signals are available to match the bandwidth constraints of the physical layer and the ATM layer. The UTOPIA level 2 supports point to multipoint configurations by introducing on addressing capability and by making a distinction between polling and selecting a device: - the ATM chip polls a specific physical layer chip by putting its address on the address bus when the Enb* line is asserted. The addressed physical layer answers the next cycle via the Clav line reflecting its status at that time. - the ATM chip selects a specific physical layer by putting its address on the address bus when the Enb* line is deasserted and asserting the Enb* line on the next cycle. The addressed physical layer chip will be the target or source of the next cell transfer.
ATM
RxADDR RxCLAV RxENB*
5 1
PHY RECEIVE
RxCLK RxDATA RxSOC RxREF*
8
ATM RECEIVE
TxADDR TxCLAV TxENB*
5 1
PHY TRANSMIT
TxCLK TxDATA TxSOC TxREF*
8
ATM TRANSMIT
D98TL329
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STLC60135
Utopia Level 2 Signals The physical chip sends cell data towards the ATM layer chip. The ATM layer chip polls the status of the fifo of the physical layer chip. The cell exchange proceeds like: a) The physical layer chip signals the availability of a cell by asserting RxClav when polled by the ATM chip. b) The ATM chips selects a physical layer chip, then starts the transfer by asserting RxEnb*. c) If the physical layer chip has data to send, it puts them on the RxData line the cycle after it sampled RxEnb* active. It also advances the offset in the cell. If the data transferred is the first byte of a cell, RxSOC is 1b at the time of the data transfer, 0b otherwise. d) The ATM chip accepts the data when they are available. If RxSOC was 1b during the transfer, it resets its internal offset pointer to the value 1, otherwise it advances the offset in the cell.
STLC60135 Utopia Level 2 MPHY Operation Utopia level 2 MPHY operation can be done by various interface schemes. The STLC60135 supports only the required mode, this mode is referred to as "Operation with 1 TxClav and 1 RxClav". PHY Device Identification The STLC60135 holds 2 PHY layer Utopia ports, one is dedicated to the fast data channel, the other one to the interleaved data channel. The associated PHY address is specified by the PHY_ADDR_x fields in the Utopia PHY address register. Beware that an incorrect address configuration may lead to bus conflicts. A feature is defined to disable (tri-state) all outputs of the Utopia interface. It is enabled by the TRI_STATE_EN bit in the Rx_interface control register.
Pin Description Utopia 2 (Receive Interface)
Name RxClav Type Meaning O Receive Cell available Usage Signals to the ATM chip that the STLC60135 has a cell ready for transfer Signals to the physical layer that the ATM chip will sample and accept data during next clock cycle Gives the timing signal for the transfer, generated by ATM layer chip. ATM cell data, from physical layer chip to ATM chip, byte wide. Identifies the cell boundary on RxData Remark Remains active for the entire cell transfer RxData and RxSOC could be tristate when RxEnb* is inactive (high)
RxEnb*
I
Receive Enable
RxClk
I
Receive Byte Clock
RxData RxSOC
O O
Receive Data (8 bits) Receive Start Cell
Indicate to the ATM layer chip that RxData contains the first valid byte of a cell.
RxAddr RxRef *
I O
Receive Address (5 bits) Use to select the port that will be active or polled Reference Clock 8kHz clock transported over the network
*Active low signal
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STLC60135
Pin Description Utopia 2 (Transmit interface)
Name TxClav Type O Meaning Transmit Cell available Transmit Enable Transmit Byte Clock Usage Signals to the ATM chip that the physical layer chip is ready to accept a cell Signals to the physical layer that TxData and TxSOC are valid Gives the timing signal for the transfer, generated by ATM layer chip. ATM cell data, to physical layer chip to ATM chip, byte wide. Identifies the cell boundary on TxData Use to select the port that will be active or polled 8kHz clock from the ATM layer chip Remark Remains active for the entire cell transfer
TxEnb* TxClk
I I
TxData TxSOC TxAddr TxRef *
I I I I
Transmit Data (8 bits) Transmit Start of Cell Transmit Address (5 bits) Reference Clock
*Active low signal
BitStream Interface The Bitstream interface is a proprietary point to point interface. The STLC60135 is the bus master of the interface. The interface is synchronous, a common clock is used. SLAP (Synchronous Link Access Protocol) Interface The SLAP interface is a point to point bitstream interface. The STLC60135 is the bus master of the interface. The interface is synchronous, a common clock (SLAP_CLOCK) is used. The basic idea is illustrated in Figure 20. The SLAP interface dumps the data of the fast and interleaved channels on 2 separate sub interfaces. The data flow from the SLAP interface must be Figure 21. Common Clock Data Transfer
enabled by the Transceiver Controller. A disabled cell interface does not dump data on its interface. Receive SLAP Interface The interface signals use 2 signal types: (refer to fig. 22) - SLR_DATA [1:0]: data pins, a byte is transferred in 4 cycles of 2 bits. The msb are transmitted first, odd bits are asserted on SLR_DATA [1]. - SLR_VAL: indicates the data transfer and the byte boundary - SLR_FRAME: indicates the start of a superframe Notice 2 SLAP interfaces are supported, one for the fast data flow, the other one for the interleaved data flow. The logic timing diagram is shown in figure 23.
Figure 22. ReceivePath, SLAP Interface
SLAP_CLOCK
SOURCE RISING CLOCK
D
Q FALLING CLOCK
D
Q SINK
DATA
2
CK QN
CK QN
EXTERNAL COMPONENT (SLAVE)
VALID
MODEM (MASTER)
D98TL332
SLAP_CLOCK
FRAME
D98TL333
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STLC60135
Figure 23. ReceiveSLAP Interface Timing
STM_CLOCK 0 1 2 3 8
minimum 8 cycles FRAME UNDEFINED UNDEFINED
VALID SLR_DATA(1) SLR_DATA(0) b7 b6 b5 b4 b3 b2 b1 b0
SLR_VAL must not repeat in a 8 clock cycle period
one byte as 4 times 2 bits
D98TL334
The implementation must guarantee that all active SLR_Valid signals must be separated by at least 8 clock cycles. Refer to Figure 23. The SLR_FRAME signals are asserted when the first pair of bits of a frame are transferred. For the fast channel a frame is defined as a superframe timebase. For the interleaved channel the frame is defined by a timebase period of 4 superframes. Both timebases are synchronized to the data flow. Transmit SLAP Interface The Transmit interface uses the following signals (refer to Figure 24) - SLT_REQ: byte request - SLT_FRAME: start of frame indication Figure 24. Interface Towards PHY Layer
CLOCK
- SLT_DATA [1:0] data pins, a byte is transferred 2 bits at the time in 4 successive clock cycles. MSB first, odd bits on SLT_DATA [1] The logical timing diagram is shown in Figure 25. The delay between Request and the associated data byte is defined as 8 cycles. The SLT_FRAME signals are asserted when the first pair of bits of a frame are transferred. For the fast channel a frame is defined as a superframe timebase. For the interleaved channel the frame is defined by a timebase period of 4 superframes. Both timebases are synchronized to the data flow and guarantee that the frame indication is asserted when the first bits of the first DMT symbol are transferred. Figure 25. Transmit SLAP Interface Timing Diagram
REQUEST
CLOCK 0 8 9 0 1 1 1 2
Request may be repeated after 4 cycles Delay Request-Data equals 8 cycles
1
STM_CLOCK
EXTERNAL COMPONENT (SLAVE)
2
DATA
MODEM (MASTER)
SLT_REQUEST
FRAME
SLT_DATA(1) SLT_DATA(0)
b7 b5 b3 b1 one byte in 4 cycles b6 b4 b2 b0
repeated each superframe/ S-frame
D98TL335
SLT_FRAME
UNDEFINED
UNDEFINED
D98TL336
Figure 26. InterfaceTiming
Tper Th Ti
CLOCK
Ts Thd
ALL INPUTS
Td
ALL OUTPUTS
D98TL337
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STLC60135
SLAP INTERFACE, AC Electrical Characteristics
Symbol Tper Th Tl Ts Thd Td Parameter Clock Period Clock High Clock Low Setup Hold Data Delay 20pF load Test Condition refer to MCLK 11 11 3 2 3 6 Min. Typ. Max. Unit ns ns ns ns ns ns
Analog Front End Control Interface The Analog Front End Interface is designed to be connected to the STLC60134 Analog Front End component. Transmit Interface The 16 bit words are multiplexed on 4 AFTXD output signals. As a result 4 cycles are needed to transfer 1 word. Refer to table 1 for the bit/pin allocation for the 4 cycles. The first of 4 cycles is identified by the CLWD signal. Refer to Figure 26. Figure 27. TransmittWord Timing Diagram
MCLK
The STLC60135 fetches the 16 bit word to be multiplexed on AFTXD from the Tx Digital FrontEnd module. Receive Interface The 16 bit receive word is multiplexed on 4 AFRXD input signals. As a result 4 cycles are needed to transfer 1 word. Refer to Table 2 for the bit / pin allocation for the 4 cycles. The first of 4 cycles is identified by the CLWD must repeat after 4 MCLK cycles.
Table 1: Transmitted Bits Assigned to Signal / Time Slot
Cycle 0 Cycle 1 Cycle 2 Cycle 3 AFTXD[0] AFTXD[1] AFTXD[2] b0 b1 b2 b3 t0 b4 b5 b6 b7 t1 b8 b9 b10 b11 t2 b12 b13 b14 b15 t3
CLWD AFTXD AFTXED
Cycle0 Cycle1 Cycle2 Cycle3
AFTXD[3] GP_OUT
D98TL320
GP_OUT
Test0 Test1 Test2 Test3
Figure 28. ReceiveWord Timing Diagram
MCLK
Table 2: Transmitted Bits Assigned to Signal / Time Slot
Cycle 0 Cycle 1 Cycle 2 Cycle 3 AFRXD[0] AFRXD[1] AFRXD[2] b0 b1 b2 b3 t0 b4 b5 b6 b7 t1 b8 b9 b10 b11 t2 b12 b13 b14 b15 t3
CLWD
AFRXD
Cycle0 Cycle1 Cycle2 Cycle3
AFRXD[3] GP_IN
D98TL321
GP_IN(0)
Test0 Test1 Test2 Test3
Figure 29. Transmit Interface
MCLK
Tv
Figure 30. ReceiveInterface
MCLK
Ts Th
AFTXD AFTXED
Tc
AFRXD
CLWD
D98TL322
D98TL323
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STLC60135
Table 3: Master Clock (MCLK) AC Electrical Characteristics
Symbol F Tper Th Parameter Clock Frequency Clock Period Clock Duty Cycle 40 Test Condition Min. Typ. 35.328 28.3 60 Max. Unit MHz ns %
Table 4: AFTXD, AFTXED, CLWD AC Electrical Characteristics
Symbol Tv Tc Parameter Data Valid Time Data Valid Time Test Condition Min. 0 0 Typ. Max. 10 10 Unit ns ns
Table 5: AFRXD AC Electrical Characteristics
Symbol Ts Th Parameter Data setup Time Data hold Time 17 19 21 23 24 25 27 28 30 31 32 33 34 35 38 39 41 42 44 Sequence Number 2 3 4 6 7 9 10 12 13 14 16 Mnemonic AD_0 AD_1 AD_2 AD_3 AD_4 AD_5 AD_6 AD_7 AD_8 AD_9 AD_10 Pin BS Type B B B B B B B B B B B 45 46 47 48 50 51 52 53 55 56 58 60 Test Condition Min. 5 5 AD_11 AD_12 PCLK AD_13 AD_14 AD_15 BE1 ALE CSB WR_RDB RDYB OBC_TYPE INTB RESETB U_RxData_0 U_RxData_1 U_RxData_2 U_RxData_3 U_RxData_4 U_RxData_5 VSS U_RxData_6 U_RxData_7 U_RxADDR_0 U_RxADDR_1 U_RxADDR_2 U_RxADDR_3 U_RxADDR_4 GP_IN_0 GP_IN_1 U_RxRefB B B I I I I I i I O Typ. Max. Unit ns ns B B I B B B I C I I O I O I B B B B B B
Tests, Clock, JTAG Interface - Mclk: Master Clock (35.328MHz) generated by VCXO - ATM receive interface, asynchronous clock generated by Utopia Master - ATM transmit interface, asynchronous clock generated by Utopia Master - ATC clock (Pclk): external asynchronous clock (synchronous with ATC in case of i960 specific interface) JTAG TP interface: Standard Test Access Port, Used with the boundary scan for chip and board testing. This JTAG TAP interface consists in 5 signals: TDI, TDO, TCK & TMS. TSRTB: Test Reset, reset the TAP controller. TRSTB is an active low signal. Table 6: Boundary Scan Chain Sequence
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STLC60135
Table 6: (continued)
Sequence Number 61 63 64 65 66 68 69 70 71 74 75 77 78 79 80 82 83 84 85 87 88 89 90 92 93 94 96 97 98 99 100 101 103 104 105 106 107 110 111 112 113 114 116 118 119 120 22/25 Mnemonic U_TxRefB U_RxCLK U_RxSOC U_RxCLAV U_RxENBB U_TxCLK U_TxSOC U_TxCLAV U_TxENBB U_TxData_7 U_TxData_6 U_TxData_5 U_TxData_4 U_TxData_3 U_TxData_2 U_TxData_1 U_TxData_0 U_TxADDR_4 U_TxADDR_3 U_TxADDR_2 U_TxADDR_1 U_TxADDR_0 SLR_FRAME_F SLR_FRAME_S SLR_DATA_S_1 SLR_DATA_S_0 SLR_DATA_S SLR_DATA_F_1 SLR_DATA_F_0 SLR_VAL_F SLAP_CLOCK SLT_FRAME_F SLT_DATA_F_1 SLT_DATA_F_0 SLT_DATA_S_1 SLT_DATA_S_0 SLT_REQ_F SLT_REQ_S SLT_FRAME_S TDI TDO TMS TCK TRSTB TESTSE GP_OUT Pin BS Type I 121 123 124 125 126 128 129 130 132 133 135 136 138 139 140 142 143 PDOWN AFRXD_0 AFRXD_1 AFRXD_2 AFRXD_3 CLWD MCLK CTRLDATA AFTXED_0 AFTXED_0 AFTXED_0 AFTXED_0 IDDq AFTXD_0 AFTXD_1 AFTXD_0 AFTXD_1 O I I I I I C O O O O O none O O O O
1 1 1
I I I I I I I I I I I I I
General purpose I/O register 2 general Purpose Register (0x040)
Field GP_IN GP_OUT Type R RW Position Length bits [0,1] [2] 2 1 Function Sampled level on pins GP_IN Output level on pins GP_OUT
bits from 3 to 15 are reserved Reset Initialization The STLC60135 supports two reset modes: - A 'hardware' reset is activated by the RESETB pin (active low). A hard reset occurs when a low input value is detected at the RESETB input. The low level must be applied for at least 1ms to guarantee a correct reset operation. All clocks and power supplies must be stable for 200ns prior to the rising edge of the RESETB signal. - 'Soft' reset activated by the controller write access to a soft reset configuration bit. The reset process takes less than 10000 MCLK clock cycles. ELECTRICAL SPECIFICATIONS Generic The values presented in the following table apply for all inputs and/or outputs unless specified otherwise. Specifically they are not influenced by the choice between CMOS or TTL levels.
none O
STLC60135
DC Electrical Characteristics (All voltages are referenced to VSS, unless otherwise specified, positive current is towards the device) IO Buffers Generic DC Characteristics
Symbol IIN IOZ IPU IPD RPU RPD Parameter Input Leakage Current Tristate Leakage Current Pull up Current Pull Down Current Pull up Resistance Pull Down Resistance Test Condition VIN = VSS, VDD no pull up / pull down VIN = VSS, VDD no pull up / pull down VIN = VSS VIN = VDD VIN = VSS VIN = VDD Min. -10 -10 -25 25 -66 66 50 50 Typ. Max. 10 10 -125 125 Unit A A mA mA K K
IO Buffers Dynamic DC Characteristics Important for transient but measured at (near) DC
Symbol CIN dl/dt Ipeak COUT Parameter Input Capacitance Current Derivative Peak Current Output Capacitance (also bidirectional and tristate drivers) Test Condition @f = 1MHz 8mA driver, slew rate control 8mA driver, no slew rate control 8mA driver, slew rate control 8mA driver, no slew rate control @f = 1MHz Min. Typ. 5 23.5 89 85 100 7 Max. Unit pF mA/ns mA/ns mA mA pF
-125
Input / Output CMOS Generic Characteristics The values presented in the following table apply for all CMOS inputs and/or outputs unless specified otherwise. CMOS IO Buffers Generic Characteristics
Symbol VIL VIH VHY VOL VOH Parameter Low Level Input Voltage High Level Input Voltage Schmitt trigger hysteresis Low Level Output Voltage High Level Output Voltage Test Condition Min. 0.8 x VDD 0.8 0.4 0.85 x VDD Typ. Max. 0.2 x VDD Unit V V V V V
slow edge < 1V/ms, only for SCHMITx IOUT = XmA* IOUT = XmA*
* The reference current is dependen on the exact buffer chosen and is a part of the buffer name. The available values are 2, 4 and 8mA. t
Input/ Output TTL Generic Characteristics The values presented in the following table apply for all TTL inputs and/or outputs unless specified otherwise
Symbol VIL VIH VILHY VIHHY VHY VOL VOH Parameter Low Level Input Voltage High Level Input Voltage Low Level Threshold, falling High Level Threshold, rising Schmitt Trigger Hysteresis Low Level Output Voltage High Level Output Voltage Test Condition Min. 2.0 0.9 1.3 0.4 2.4 Typ. Max. 0.8 1.35 1.9 0.7 0.4 Unit V V V V V V V
slow edge < 1V/ms slow edge < 1V/ms slow edge < 1V/ms IOUT = XmA* IOUT = XmA*
* The reference current is dependen on the exact buffer chosen and is a part of the buffer name. The available values are 2, 4 and 8mA. t
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STLC60135
PQFP144 PACKAGE MECHANICAL DATA
DIM. MIN. A A1 A2 B C D D1 D3 e E E1 E3 L L1 K 0.65 30.95 27.90 0.25 3.17 0.22 0.13 30.95 27.90 31.20 28.00 22.75 0.65 31.20 28.00 22.75 0.80 1.60 0(min.), 7(max.) 0.95 0.026 31.45 28.10 1.219 1.098 3.42 3.67 0.38 0.23 31.45 28.10 mm TYP. MAX. 4.07 0.010 0.125 0.009 0.005 1.219 1.098 1.228 1.102 0.896 0.026 1.228 1.102 0.896 0.031 0.063 0.037 1.238 1.106 0.135 0.144 0.015 0.009 1.238 1.106 MIN. inch TYP. MAX. 0.160
D D1 A D3 A1 108 10 9 73 72
0. 10mm .004 Sea ting Plan e
A2
B
E3
E1
144 1 e 36
37 C
L1
E
L
K
PQFP14 4
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B
STLC60135
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics ToscaTM is trademark of STMicroelectronics (c) 1999 STMicroelectronics and Alcatel Alsthom, Paris - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com
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